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Abstract: Over the past decade, a pair of instructions called load-linked (LL) and store-conditional (SC) have emerged as the most suitable synchronization instructions for the design of lock-free algorithms. However, current architectures do not support these instructions; instead, they support either CAS (e.g., UltraSPARC, Itanium, Pentium) or restricted versions of LL/SC (e.g., POWER4, MIPS, Alpha). Thus, there is a gap between what algorithm designers want (namely, LL/SC) and what multiprocessors actually support (namely, CAS or restricted LL/SC). To bridge this gap, this thesis presents a series of efficient, wait-free algorithms that implement LL/SC from CAS or restricted LL/SC.

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   Srdjan Petrovic, "Efficient Wait-Free Algorithms for Implementing LL/SC Objects." Dartmouth Computer Science Technical Report TR2005-556, August 2005.

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