BIB-VERSION:: CS-TR-v2.0
ID:: ncstrl.dartmouthcs//TR2005-556
ENTRY:: August 18, 2005
ORGANIZATION:: Dartmouth College, Computer Science
TITLE:: Efficient Wait-Free Algorithms for Implementing LL/SC Objects
TYPE:: Technical Report (paper)
REVISION:: 1
AUTHOR:: Petrovic, Srdjan
DATE:: August 2005
RETRIEVAL:: For a paper copy, email <reports@cs.dartmouth.edu>
RETRIEVAL:: For a paper copy, write to
       Technical Report Librarian
       Department of Computer Science
       Dartmouth College
       6211 Sudikoff Laboratory
       Hanover, NH 03755-3510
       USA
RETRIEVAL:: PDF at http://www.cs.dartmouth.edu/reports/TR2005-556.pdf
ABSTRACT:: 
Over the past decade, a pair of instructions called load-linked (LL)
and store-conditional (SC) have emerged as the most suitable
synchronization instructions for the design of lock-free algorithms.
However, current architectures do not support these instructions;
instead, they support either CAS (e.g., UltraSPARC, Itanium, Pentium)
or restricted versions of LL/SC (e.g., POWER4, MIPS, Alpha).
Thus, there is a gap between what algorithm designers want (namely, LL/SC)
and what multiprocessors actually support (namely, CAS or restricted LL/SC).
To bridge this gap, this thesis presents a series of efficient, wait-free
algorithms that implement LL/SC from CAS or restricted LL/SC.
END:: ncstrl.dartmouthcs//TR2005-556