BIB-VERSION:: CS-TR-v2.0
ID:: ncstrl.dartmouthcs//TR86-106
ENTRY:: January 20, 1995
ORGANIZATION:: Dartmouth College, Computer Science
TITLE:: Algorithms for Iterative Array Multiplication
TYPE:: Technical Report (paper)
REVISION:: 1
AUTHOR:: Nakamura, Shinji
NOTE:: The 'January' in DATE is an arbitrary placeholder.
DATE:: January 1986
RETRIEVAL:: For a paper copy, email <reports@cs.dartmouth.edu>
RETRIEVAL:: For a paper copy, write to
       Technical Report Librarian
       Department of Computer Science
       Dartmouth College
       6211 Sudikoff Laboratory
       Hanover, NH 03755-3510
       USA
RETRIEVAL:: PDF at http://www.cs.dartmouth.edu/reports/TR86-106.pdf
ABSTRACT::
	Algorithms for the parallel multiplication of two n bit binary
numbers by an iterative array of logic cells are discussed.  The
regular interconnection structures of the multiplier array cell
elements, which are ideal for VLSI implementation, are described.  The
speed and hardware complexity of two new iterative array algorithms,
both of which require n cell delays for one n by n bit multiplication,
are compared with a straight-forward iterative array algorithm having
a 2n cell delay and its higher radix version having an n cell delay.
END:: ncstrl.dartmouthcs//TR86-106