BIB-VERSION:: CS-TR-v2.0
ID:: ncstrl.dartmouthcs//TR91-161
ENTRY:: January 20, 1995
ORGANIZATION:: Dartmouth College, Computer Science
TITLE:: On Minimizing Hardware Overhead for Exhaustive Circuit Testability
TYPE:: Technical Report (paper)
REVISION:: 1
AUTHOR:: Kagaris, Dimitrios
AUTHOR:: Makedon, Fillia
NOTE:: The 'January' in DATE is an arbitrary placeholder.
DATE:: January 1991
RETRIEVAL:: For a paper copy, email <reports@cs.dartmouth.edu>
RETRIEVAL:: For a paper copy, write to
       Technical Report Librarian
       Department of Computer Science
       Dartmouth College
       6211 Sudikoff Laboratory
       Hanover, NH 03755-3510
       USA
RETRIEVAL:: PDF at http://www.cs.dartmouth.edu/reports/TR91-161.pdf
ABSTRACT::
	Exhaustive built-in self testing is given much attention as a
viable technique in the context of VLSI technology.  In this paper, we
present heuristic in order to make exhaustive testing of combinational
circuits practical.  The goal is to place a small number of register
cells on the nets of the input circuit so that the input dependency of
combinational elements in the circuit is less than a small given
integer k.  Our heuristic guarantees that each output can be
individually tested with 2k test patterns and can be used as a
subroutine to generat efficient test patterns to test all the outputs
of the circuit simultaneously.  For example, we can connect the
register cells in a Linear Feedback Shift Register(LFSR).
  Minimizing the number of the inserted register cells reduces the
hardware overhead as well as the upper bound on the number of test
patterns generated.  A heuristic approach has been proposed only for
the case when an element in the circuit schematic denotes a boolean
gate.  An element may, however, also be used to represent a
combinatorial circuit model.  Our heuristic applies to this case as
well.  Extensive experimentation indicates that the proposed technique
is very efficient.
END:: ncstrl.dartmouthcs//TR91-161