@TechReport{Dartmouth:TR91-161,
  author = {Dimitrios Kagaris and Fillia Makedon},
  title = {{On Minimizing Hardware Overhead for Exhaustive Circuit Testability}},
  institution = {Dartmouth College, Computer Science},
  address = {Hanover, NH},
  number = {PCS-TR91-161},
  year = {1991},
  URL = {http://www.cs.dartmouth.edu/reports/TR91-161.pdf},
  abstract = {
    	Exhaustive built-in self testing is given much attention as a
    viable technique in the context of VLSI technology.  In this paper, we
    present heuristic in order to make exhaustive testing of combinational
    circuits practical.  The goal is to place a small number of register
    cells on the nets of the input circuit so that the input dependency of
    combinational elements in the circuit is less than a small given
    integer k.  Our heuristic guarantees that each output can be
    individually tested with 2k test patterns and can be used as a
    subroutine to generat efficient test patterns to test all the outputs
    of the circuit simultaneously.  For example, we can connect the
    register cells in a Linear Feedback Shift Register(LFSR).
      Minimizing the number of the inserted register cells reduces the
    hardware overhead as well as the upper bound on the number of test
    patterns generated.  A heuristic approach has been proposed only for
    the case when an element in the circuit schematic denotes a boolean
    gate.  An element may, however, also be used to represent a
    combinatorial circuit model.  Our heuristic applies to this case as
    well.  Extensive experimentation indicates that the proposed technique
    is very efficient.
  }
}