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A viable technique  in built-in self-test (BIST) is to generate test patterns pseudo-exhaustively by using linear feedback shift registers (LFSR's). The goal is to find an appropriate primitive polynomial of degree d that will generat 2d test patterns in order to exercise all circuit outputs simultaneously. In an attempt to reduce the degree d of the polynomial the following strategy was proposed in [6,5]. In the first phase, partition the circuit into segments by inserting a small number of register cells, so that the input dependency of any circuit element in the segments is no more than d. Then, obain an appropriate primitive polynomial of degree d by inserting additional register cells. In  we have proposed a heuristic for phase one that does not necessarily partition the circuit. Extensive experimentation has shown that this results in a considerably smaller cell overhead.
In this paper we extend our heuristic in , so that the minimization of the number of register cells is done in conjunction with a quantity that naturally reflects the difficulty of deriving an appropriate primitive polynomial of degree d. Experimentation shows that the proposed heuristic results again in an overall smaller number of register cells than a partition based approach and in an efficient framework for test pattern generation.
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Dimitrios Kagaris and Fillia Makedon, "A Metric Towards Efficient Exhaustive Test Pattern Generation." Dartmouth Computer Science Technical Report PCS-TR91-162, 1991.
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