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Avoiding Conflicts Dynamically in Direct Mapped Caches with Minimal Hardware Support
Peter N. DeSantis
Dartmouth PCS-TR98-339

Abstract:

The memory system is often the weakest link in the performance of today's computers. Cache design has received increasing attention in recent years as increases in CPU performance continues to outpace decreases in memory latency.

Bershad et al. proposed a hardware modification called the Cache Miss Lookaside buffer which attempts to dynamically identify data which is conflicting in the cache and remap pages to avoid future conflicts. In a follow-up paper, Bershad et al. tried to modify this idea to work with standard hardware but had less success than with their dedicated hardware.

In this thesis, we focus on a modification of these ideas, using less complicated hardware and focusing more on sampling policies. The hardware support is reduced to a buffer of recent cache misses and a cache miss counter. Because determination of remapping candidates is moved to software, sampling policies are studied to reduce overhead which will most likely fall on the OS. Our results show that sampling can be highly effective in identifying conflicts that should be remapped. Finally, we show that the theoretical performance of such a system can compare favorably with more costly higher associativity caches.

Note: Senior Honors Thesis. Advisor: Tom Cormen.


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   Peter N. DeSantis, "Avoiding Conflicts Dynamically in Direct Mapped Caches with Minimal Hardware Support." Dartmouth Computer Science Technical Report PCS-TR98-339, June 1998.


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