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http://www.cs.dartmouth.edu/~sws/abstracts/ls01.shtml     Last modified: 08/27/03 11:56:52 AM

M. Lindemann, S.W. Smith.
``Improving DES Hardware Throughput for Short Operations.''
USENIX Security Symposium, August 2001.

Abstract

Over the last several years, our research team built a commercially-offered secure coprocessor that, besides other features, offers high-speed DES: over 20 megabytes/second. However, it obtains these speeds only on operations with large data lengths. For DES operations on short data (e.g., 8-80 bytes), our commercial offering was benchmarked at less than 2 kilobytes/ second. The programmability of our device enabled us to investigate this issue, identify and address a series of bottlenecks that were not initially apparent, and ultimately bring our short-DES performance close to 3 megabytes/second. This paper reports the results of this real-world systems exercise in hardware cryptographic acceleration-and demonstrates the importance of, when designing specialty hardware, not overlooking the software aspects governing how a device can be used.

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